The present invention generally relates to the field of semiconductors, and more particularly relates to a method of fabricating strained FinFET semiconductor devices.
Strain engineering is highly desired for boosting CMOS performance Tensile strain is beneficial for nFET and compressive strain is beneficial for pFET.
Strained high germanium percentage (Ge %) silicon germanium (SiGe) channel (compressive) and silicon (Si) channel (tensile) grown on strain relaxation buffer (SRB) substrate layer have been touted as a device option for continued scaling CMOS (complementary metal-oxide-semiconductor) technology beyond 7 nm node.
However, when SiGe or Si fins are cut (e.g., etched) into desired lengths to meet the design requirements, strain relaxes (and strain loss occurs) at fin ends. The loss of strain at SiGe or Si fin ends causes device degradation and variation.
Therefore, there is a need to fabricate SiGe fins and Si fins to prevent/recover strain relaxation at fin ends.